The Zynq Book【2025|PDF|Epub|mobi|kindle电子书版本百度云盘下载】

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CHAPTER 1 Introduction1

1.1 System-on-Chip with Zynq2

1.2 Simple Anatomy of an Embedded SoC5

1.3 Design Reuse7

1.4 Raising the Abstraction Level7

1.5 SoC Design Flow8

1.6 Practical Elements10

1.7 About This Book10

1.8 References12

PART A Getting to Know Zynq13

CHAPTER 2 The Zynq Device （“What is it？”）15

2.1 Processing System16

2.1.1 Application Processing Unit （APU）17

2.1.2 A Note on the ARM Model20

2.1.3 Processing System External Interfaces21

2.2 Programmable Logic22

2.2.1 The Logic Fabric23

2.2.2 Special Resources：DSP48E1s and Block RAMs25

2.2.3 General Purpose Input/Output28

2.2.4 Communications Interfaces29

2.2.5 Other Programmable Logic External Interfaces29

2.3 Processing System — Programmable Logic Interfaces30

2.3.1 The AXI Standard30

2.3.2 AXI Interconnects and Interfaces31

2.3.3 EMIO Interfaces34

2.3.4 Other PL-PS Signals34

2.4 Security35

2.4.1 Secure Boot35

2.4.2 Hardware Support36

2.4.3 Runtime Security36

2.5 Zynq-7000 Family Members39

2.6 Chapter Review40

2.7 Architecture Reference Guide41

2.8 References44

CHAPTER 3 Designing with Zynq （“How do I work with it？”）47

3.1 Getting Started48

3.1.1 Obtaining Design Tools48

3.1.2 Design Tool Editions and Licensing49

3.1.3 Design Tool Functionality50

3.1.4 Third Party Tools51

3.1.5 System Setup and Requirements51

3.2 An Outline of the Design Flow53

3.2.1 Requirements and Specification54

3.2.2 System Design54

3.2.3 Hardware Development and Testing55

3.2.4 Software Development and Testing58

3.2.5 System Integration and Testing60

3.3 SoC Design Teams60

3.4 System-Level IP-Focused Design with Vivado62

3.5 The ISE and Vivado Design Suites64

3.5.1 Features Comparison64

3.5.2 Upgrading to Vivado66

3.6 Development Boards67

3.6.1 Zynq-7000 SoC ZC702 Evaluation Kit67

3.6.2 Zynq-7000 SoC Video ＆ Imaging Kit69

3.6.3 Zynq-7000 ZC706 Evaluation Kit69

3.6.4 ZedBoard69

3.6.5 ZYBO69

3.6.6 Third Party Boards70

3.6.7 Accessories and Expansions71

3.6.8 Working with Development Boards72

3.7 Support and Documentation72

3.8 Chapter Review72

3.9 References73

CHAPTER 4 Device Comparisons （“Why do I need Zynq？”）77

4.1 Device Selection Criteria78

4.2 Comparison A：Zynq versus FPGA80

4.2.1 MicroBlaze Processor80

4.2.2 MicroBlaze MicroController System84

4.2.3 PicoBlaze85

4.2.4 ARM Cortex-M185

4.2.5 Other Processor Types85

4.2.6 Summary Comments87

4.3 Comparison B：Zynq versus Standard Processor89

4.3.1 Processor Operation89

4.3.2 Execution Profiling92

4.3.3 Summary Comments94

4.4 Comparison C：Zynq versus a Discrete FPGA-Processor Combination94

4.5 Exploiting the Zynq Architecture and Design Flow96

4.6 Chapter Review98

4.7 References99

CHAPTER 5 Applications and Opportunities（“What can I do with it？”）101

5.1 An Overview of Applications102

5.1.1 Automotive102

5.1.2 Communications102

5.1.3 Defence and Aerospace103

5.1.4 Robotics，Control and Instrumentation103

5.1.5 Image and Video Processing104

5.1.6 Medical105

5.1.7 High Performance Computing （HPC）105

5.1.8 Others and Future Applications105

5.2 When Can Zynq Really Help…？106

5.3 Communications：Software Defined Radio （SDR）107

5.3.1 Trends in Wireless Communications107

5.3.2 Introducing Software Defined Radio （SDR）108

5.3.3 SDR Implementation and Enabling Technologies108

5.3.4 Cognitive Radio110

5.4 Smart Systems and Smart Networks111

5.4.1 What is a Smart System？111

5.4.2 Examples of Smart Systems112

5.4.3 Smart Networks：Communications for Smart Systems114

5.4.4 Related Concepts115

5.5 Image and Video Processing，and Computer Vision115

5.5.1 Image and Video Processing115

5.5.2 Computer Vision116

5.5.3 Levels of Abstraction117

5.5.4 Implementation of Image Processing Systems118

5.5.5 Computer Vision on Zynq Example：Road Sign Recognition120

5.6 Dynamic System-on-Chip121

5.6.1 Run Time System Flexibility121

5.6.2 Dynamic Partial Reconfiguration （DPR）121

5.6.3 DPR Application Examples122

5.6.4 Benefits of DPR124

5.7 Further Opportunities：the Zynq ‘EcoSystem’125

5.7.1 What is the Ecosystem？125

5.7.2 What is the Opportunity？126

5.8 Chapter Review128

5.9 References128

CHAPTER 6 The ZedBoard133

6.1 Introducing Zed133

6.2 ZedBoard System Architecture134

6.3 The Design Flow for ZedBoard136

6.4 Getting Started with the ZedBoard137

6.4.1 What’s in the Box？137

6.4.2 Hardware Setup137

6.4.3 Programming the ZedBoard138

6.5 MicroZed142

6.6 Documentation，Tutorials and Support142

6.6.1 Documentation about the ZedBoard142

6.6.2 Demonstrations and Tutorials143

6.6.3 Online Courseware143

6.6.4 Other ZedBoard Resources and Support144

6.7 ZedBoard.org Community144

6.7.1 Community Projects144

6.7.2 Blogs145

6.7.3 Support Forums145

6.8 Chapter Review145

6.9 References146

CHAPTER 7 Education，Research and Training147

7.1 Technology Trends and SoC Education148

7.2 University Teaching with Zynq149

7.2.1 Teaching with Xilinx Tools and Boards149

7.2.2 Digital Design and FPGA Teaching150

7.2.3 Computer Science150

7.2.4 Embedded Systems and SoC Design150

7.2.5 Algorithm Implementation （e.g.Signal，Image，and Video Processing）151

7.2.6 Design Reuse152

7.2.7 New and Emerging Design Methods153

7.2.8 Sensing，Robotics，and Prototyping154

7.2.9 An Example Course154

7.3 Projects and Competitions155

7.4 Academic Research156

7.5 The Xilinx University Program （XUP）158

7.5.1 Introducing XUP158

7.5.2 Software Support and Licenses158

7.5.3 XUP Development and Teaching Boards159

7.5.4 XUP Workshops and Training Materials159

7.5.5 Technical Support for Universities160

7.5.6 Eligibility160

7.5.7 Getting in Touch with XUP160

7.6 Training for Industry160

7.6.1 Courses and Authorised Training Providers160

7.6.2 Other Resources161

7.6.3 Online Videos161

7.7 Chapter Review161

7.8 References162

CHAPTER 8 First Designs on Zynq165

8.1 Software Installation Guide166

8.2 Aims and Outcomes166

8.3 Overview of Exercise 1A166

8.4 Overview of Exercise 1 B167

8.5 Overview of Exercise 1 C168

8.6 Possible Extensions169

8.7 What Next？169

8.8 References169

PART B Zynq SoC ＆ Hardware Design171

CHAPTER 9 Embedded Systems and FPGAs173

9.1 What is an Embedded System？173

9.1.1 Applications174

9.1.2 Generic Embedded System Architecture175

9.2 Processors176

9.2.1 Co-processors177

9.2.2 Processor Cache178

9.2.3 Execution Cycles180

9.2.4 Interrupts183

9.3 Buses184

9.3.1 System and Peripheral Buses185

9.3.2 Bus Masters and Slaves186

9.3.3 Bus Arbitration186

9.3.4 Memory Access187

9.3.5 Bus Bandwidth188

9.4 Chapter Review189

9.5 References189

CHAPTER 10 Zynq System-on-Chip Design Overview191

10.1 Interfacing and Signals192

10.1.1 PS-PL AXI Interfaces192

10.1.2 PL Co-Processing Interfaces193

10.1.3 Interrupt Interface196

10.2 Interconnects197

10.2.1 Interconnect Features197

10.2.2 Interconnects，Masters and Slaves198

10.2.3 Connectivity199

10.2.4 AXI HP Interfaces200

10.2.5 AXI ACP Interface202

10.2.6 AXI GP Interfaces202

10.3 Memory202

10.3.1 Memory Interfaces203

10.3.2 On-Chip Memory （OCM）208

10.3.3 Memory Map210

10.4 Interrupts211

10.4.1 Interrupt Signals212

10.4.2 Generic Interrupt Controller （GIC）212

10.4.3 Interrupt Sources213

10.4.4 Interrupt Prioritisation and Handling217

10.4.5 Further Reading218

10.5 Chapter Review219

10.6 References219

CHAPTER 11 Zynq System-on-Chip Development221

11.1 Hardware/Software Partitioning221

11.2 Profiling224

11.3 Software Development Tools226

11.3.1 Software Tools226

11.3.2 Hardware Configuration Tools227

11.3.3 Software Development Kit （SDK）228

11.3.4 Microprocessor Debugger228

11.3.5 Sourcery CodeBench Lite Edition for Xilinx Cortex-A9 Compiler Toolchain229

11.3.6 Logic Analysers229

11.3.7 System Generator for DSP229

11.4 Chapter Review230

11.5 References230

CHAPTER 12 Next Steps in Zynq SoC Design231

12.1 Prerequisites231

12.2 Aims and Outcomes232

12.3 Overview of Exercise 2A232

12.4 Overview of Exercise 2B232

12.5 Overview of Exercise 2C233

12.6 Overview of Exercise 2D234

12.7 Possible Extensions235

12.8 What Next？236

CHAPTER 13 IP Block Design237

13.1 Overview237

13.2 Industry Trends and Philosophy239

13.3 IP Core Design Methods240

13.3.1 HDL240

13.3.2 System Generator241

13.3.3 HDL Coder241

13.3.4 Vivado High-Level Synthesis243

13.3.5 Choosing the Right IP Creation Method244

13.4 Simulation and Documentation244

13.4.1 Simulation244

13.4.2 Documentation249

13.5 Chapter Review252

13.6 References252

CHAPTER 14 Spotlight on High-Level Synthesis255

14.1 High-Level Synthesis Concepts256

14.1.1 What is High-Level Synthesis （HLS）？256

14.1.2 Motivations for High-Level Synthesis257

14.1.3 Design Metrics and Hardware Architectures259

14.2 Development of HLS Tools260

14.3 HLS Source Languages262

14.3.1 C262

14.3.2 C++263

14.3.3 SystemC263

14.3.4 Other Languages for High-Level Synthesis264

14.4 Introducing Vivado HLS264

14.4.1 What Does Vivado HLS Do？264

14.4.2 Vivado HLS Design Flow267

14.4.3 C Functional Verification and C/RTL Cosimulation269

14.4.4 Implementation Metrics and Considerations271

14.4.5 Overview of the High-Level Synthesis Process272

14.4.6 Solutions：Exploring the Design Space276

14.4.7 Vivado HLS Library Support277

14.5 HLS in the Design Flow for Zynq277

14.6 Chapter Review278

14.7 References278

CHAPTER 15 Vivado HLS：A Closer Look281

15.1 Anatomy of a Vivado HLS Project282

15.2 Vivado HLS User Interfaces283

15.2.1 Graphical User Interface284

15.2.2 Command Line Interface （CLI）286

15.3 Data Types287

15.3.1 C and C++ Native Data Types287

15.3.2 Vivado HLS Arbitrart Precision Data Types for C and C++289

15.3.3 Arbitrary Precision Types for SystemC292

15.3.4 Floating Point Data Types and Operators294

15.3.5 Validation of Arbitrary Precision Models294

15.4 Interface Specification and Synthesis295

15.4.1 C/C++ Function Definition295

15.4.2 Synthesis of Port-Level Interfaces296

15.4.3 Port Interface Protocol Types298

15.4.4 Synthesis of Port Interface Protocols300

15.4.5 Block-Level Interface Ports and Protocols302

15.4.6 Interface Synthesis Directives304

15.4.7 Manual Interface Specification308

15.5 Algorithm Synthesis309

15.5.1 Implementation Metrics and Constraints309

15.5.2 Data Types311

15.5.3 Pipelining311

15.5.4 Dataflow316

15.5.5 Algorithm Case Study：Loops319

15.5.6 Arrays327

15.6 Design Evaluation and Optimisation328

15.6.1 Design Constraints328

15.6.2 Synthesis Directives329

15.6.3 Statistics and Reports329

15.6.4 Design Iterations and Optimisation329

15.7 Exporting from Vivado HLS330

15.7.1 Vivado IP Catalog （IP-XACT Format）330

15.7.2 System Generator for DSP330

15.7.3 Pcore for XPS330

15.8 Chapter Review331

15.9 References331

CHAPTER 16 Designing With Vivado High Level Synthesis333

16.1 Prerequisites333

16.2 Aims and Outcomes333

16.3 Overview of Exercise 3A334

16.4 Overview of Exercise 3B334

16.5 Overview of Exercise 3C334

16.6 Possible Extensions335

16.7 What Next？335

CHAPTER 17 IP Creation337

17.1 Aims and Outcomes337

17.2 Overview of Exercise 4A338

17.3 Overview of Exercise 4B338

17.4 Overview of Exercise 4C339

17.5 Possible Extensions340

17.6 What Next？341

CHAPTER 18 IP Reuse and Integration343

18.1 Overview343

18.2 System Design — A System-Level Approach344

18.3 IP-XACT346

18.4 IP Libraries346

18.4.1 Vivado IP Catalog346

18.4.2 Third-Party347

18.4.3 Custom IP349

18.5 IP Integration349

18.5.1 IP Integrator349

18.5.2 IP Packager349

18.6 Chapter Review351

18.7 References351

CHAPTER 19 AXI Interfacing353

19.1 Development of AXI353

19.2 Variations of AXI4354

19.3 AXI Architecture354

19.3.1 Address Channels356

19.3.2 Write Data Channel356

19.3.3 Read Data Channel356

19.3.4 Write Response Channel356

19.4 Examples of Applications356

19.5 AXI Transactions358

19.5.1 AXI Write-Burst Transaction358

19.5.2 AXI Read-Burst Transaction358

19.6 AXI in the Xilinx Toolflow360

19.7 Summary364

19.8 References364

CHAPTER 20 Adventures with IP Integrator365

20.1 Aims and Outcomes366

20.2 Exercise 4A367

20.3 Exercise 4B367

20.4 Exercise 4C368

20.5 Possible Extensions368

20.6 What Next？368

PART C Operating Systems ＆ System Integration369

CHAPTER 21 Introduction to Operating Systems on Zynq371

21.1 Why Use an Embedded Operating System？371

21.1.1 Reducing Time to Market371

21.1.2 Make Use of Existing Features372

21.1.3 Reduce Maintenance and Development Costs373

21.2 Choosing the Right Type of Operating System373

21.2.1 Standalone Operating Systems374

21.2.2 Real-Time Operating Systems （RTOS）374

21.2.3 Other Embedded Operating Systems375

21.2.4 Further Considerations377

21.3 Applications377

21.4 Multi-Processor Systems378

21.5 Zynq Operating Systems379

21.5.1 Linux379

21.5.2 RTOS382

21.5.3 Further Operating Systems382

21.6 Chapter Review383

21.7 References383

CHAPTER 22 Linux：An Overview385

22.1 A Brief History385

22.2 Linux System Overview386

22.3 Licensing387

22.3.1 GNU General Public licence388

22.4 Development Tools and Resources389

22.4.1 Virtual Machines389

22.4.2 Version Control391

22.4.3 Git392

22.4.4 Debugging Linux393

22.5 Chapter Review395

22.6 References396

CHAPTER 23 The Linux Kernel397

23.1 Linux Kernel Hierarchy397

23.2 System Call Interface398

23.3 Memory Management400

23.3.1 Virtual Memory400

23.3.2 High and Low Memory401

23.4 Process Management401

23.4.1 Process Representation402

23.4.2 Process Creation，Scheduling and Destruction402

23.5 File System404

23.5.1 Linux File Systems404

23.5.2 Virtual File System405

23.6 Architecture-Dependent Code406

23.7 Linux Device Drivers406

23.7.1 A Note on Mechanisms Vs.Policies407

23.7.2 Module/Device Classification407

23.8 Chapter Review408

23.9 References408

CHAPTER 24 Linux Booting409

24.1 Overview409

24.2 Stages of the Desktop Linux Boot Process411

24.2.1 BIOS411

24.2.2 First-Stage Bootloader （FSBL）411

24.2.3 Second-Stage Bootloader （SSBL）412

24.2.4 Kernel413

24.2.5 Init413

24.3 Booting Zynq414

24.3.1 Zynq Boot Files416

24.3.2 Stage-0 （Boot ROM）417

24.3.3 Stage-1 （First-Stage Bootloader）419

24.3.4 Stage-2 （Second-Stage Bootloader）425

24.4 Chapter Review425

24.5 References426

Postscript427

Glossary429

List of Acronyms439

Index451